1. Field of the Invention
The present invention relates, in general, to a method for the fabrication of dynamic random access memory (hereinafter referred to as "DRAM") capacitor and, more particularly, to an improvement in both capacitance and topology of the capacitor along with the method.
2. Description of the Prior Art
Recent high integration trend of DRAM inevitably involves a reduction in cell dimension. However, such a reduction in cell dimension results in a difficulty to form capacitors having a sufficient capacitance. This is because the capacitance is in proportion to the surface area of capacitor. In a case of a DRAM device constituted by one MOS transistor and one capacitor, in particular, it is important to reduce the cell dimension and yet obtain a high capacitance of the capacitor, for the high integration of the DRAM device.
Capacitance of such a capacitor formed on a reduced area can be expressed by the following equation: EQU Capacitance (C) .varies. Dielectric Constant.times.Surface Area+Thickness of *Dielectric Layer
Many research and development efforts have been made to increase the capacitance. For example, there have been known use of a dielectric material exhibiting a high dielectric constant, formation of a thin dielectric layer, formation of a capacitor having an increased surface area. However, each of these techniques has its problem. In other words, although various materials have been proposed as the dielectric material exhibiting a high dielectric constant, they have not been confirmed in reliance and thin film characteristic such as junction breakdown voltage. The reduction in thickness of dielectric layer results in damage of the dielectric layer, severely affecting the reliance of capacitor. For increasing the surface area of capacitor, a complex process should be used. Furthermore, the increase in surface area results in a degradation in integration degree.
Generally, existing capacitors include a conduction layer comprised of a polysilicon layer and a dielectric layer comprised of an oxide film, a nitride film or a combination thereof. For an increase in surface area of capacitor, the polysilicon layer has a multi-layer structure and spacers having a pin shape, a cylindrical shape or a rectangular frame shape extending through the multi-layer structure to connect layers of the multi-layer structure.
Now, a description will be made in conjunction with the pin-shaped capacitor. For fabricating the pin-shaped capacitor, first, an interlayer insulating film and a first planarizing layer superior in fluidity are sequentially formed over a semiconductor substrate having a field oxide film at its element isolation region and MOS field effect transistor (hereinafter referred to as "MOSFET") type elements such as a gate oxide film and a gate at its active region, thereby planarizing the semiconductor substrate. Thereafter, a first conduction layer, a first insulating film, a second conduction layer and a second insulating film are sequentially formed over the first planarizing layer.
Subsequently, all the layers formed over the semiconductor substrate are sequentially removed at their portions disposed over a portion of the semiconductor substrate defined as the active region to be in contact with a capacitor, thereby forming a contact hole. A third conduction layer is coated over the resulting structure so as to fill the contact hole. Over the third conduction layer, a third insulating film is formed. Thus, a pin-shaped capacitor is obtained which has a structure of vertically connecting the conduction layers with one another.
Although this multi-layer structure described allows the conventional pin-shaped capacitor to have an increased surface area, it still has an insufficient capacitance due to the high integration of a DRAM device employing it. As a result, the DRAM device encounters a degradation in reliance of its operation. Since the capacitor had the multi-layer structure, an increase in topology occurs, thereby causing subsequent layers to be degraded in capability of coating steps.
On the other hand, in fabrication of the cylindrical capacitor, a conduction layer is coated over a planarizing layer of a semiconductor substrate structure obtained after formation of a contact hole through which an active region of the semiconductor substrate to be in contact with a capacitor, so as to fill the contact hole. An insulating film pattern having a cylindrical bar shape is then formed on a portion of the conduction layer.
Although the cylindrical capacitor has an advantage of a reduced topology, as compared with the pin-shaped capacitor, it encounters a degradation in integration degree because it should occupy a large area for obtaining a sufficient capacitance, due to its small surface area. Of course, the capacitance may be increased by repeatedly forming cylindrical side walls to be shaped into a plurality of concentric circles. In this case, however, the overall fabrication becomes complex.